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motorola semiconductor technical data MC68HC05P9AD/d rev. 0 addendum to hcmos microcontroller unit t echnical data mc68hc05p9 this document contains information on a new product. speci?cations and information herein are subject to change without notice. this addendum provides additions and corrections to the mc68hc05p9 technical data , rev. 0 (motorola document number mc68hc05p9/d). 1. page 1-1, section 1.1 features change the third bulleted item as follows: from: ? 2112 bytes of user rom including 16 user vector locations to : ? 2104 bytes of user rom including 8 user vector locations
motorola MC68HC05P9AD/d 2. page 2-7, section 2.6.3 port c and analog-to-digital converter replace the second paragraph with the following: from: when the a/d converter is enabled, pc7 becomes v rh , and pc6Cpc3 become an3Can0 (analog inputs 3C0). the values of ch1 and ch0 in the a/d status and control register (adscr) select one of the four pins as the input to the a/d converter. when the a/d converter is enabled, a digital read of port c gives a logical zero from the selected analog input pin. a digital read of port cs remaining pins gives their correct digital values. v rh is the positive (high) reference voltage for the a/d converter. v ss is the negative (low) reference voltage. a reset turns off the a/d converter and con?gures port c as a general-purpose i/o port. (refer to section 8 analog-to-digital converter .) to : when the a/d converter is enabled, pc7 becomes v rh , and pc6Cpc3 become an3Can0 (analog inputs 3C0). the values of ch1 and ch0 in the a/d status and control register (adscr) select one of the four pins as the input to the a/d converter. unused analog inputs can be used as digital inputs, but no analog input can be used as a digital output while the adc is on. only pins pc0Cpc2 can be used as digital outputs when the adc is on. when the a/d converter is enabled, a digital read of port c gives a logical zero from the selected analog input pin. a digital read of the remaining port c pins gives their correct digital values. v rh is the positive (high) reference voltage for the a/d converter. v ss is the negative (low) reference voltage. a reset turns off the a/d converter and con?gures port c as a general-purpose i/o port. (refer to section 8 analog-to-digital converter .) 3. page 3-23, table 3-13. opcode map replace the opcode map with the opcode map on page 3. the new opcode map contains data corrections for the following opcodes: opcode mnemonic opcode mnemonic 13 bclr1 68 asl/lsl 25 bcs/blo 69 rol 38 asl/lsl 6a dec 48 asla/lsla 6c inc 50 negx 6d tst 58 aslx/lslx 6f clr 78 asl/lsl
MC68HC05P9AD/d motorola table 3-13. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 ta x 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb
motorola MC68HC05P9AD/d 4. page 4-1, section 4.1 resets change the ?rst bulleted item in the second paragraph as follows: from: ? all implemented data direction register bits are cleared to logical zero, so the corresponding i/o pins become high-impedance inputs. to : ? all implemented data direction register bits are cleared to logical zero, so the corresponding i/o pins become high-impedance inputs. (when an external reset or power-on reset occurs, i/o port pins become high-impedance inputs even if the system clock is absent.) 5. page 4-2, section 4.1.3 computer operating properly (cop) watchdog reset in the fourth sentence in the ?rst paragraph, change the 64 ms to 65.5 ms as follows: from: the cop system is implemented with an 18-stage ripple counter that provides a timeout period of 64 ms at an internal clock rate of 2 mhz. to : the cop system is implemented with an 18-stage ripple counter that provides a timeout period of 65.5 ms at an internal clock rate of 2 mhz.
MC68HC05P9AD/d motorola 6. page 4-2, section 4.1.3 computer operating properly (cop) watchdog reset replace the second paragraph as follows: from: the write-only cop register is used to prevent a cop timer reset. this location contains user-de?ned rom data. figure 4-1 shows the cop register. to : the write-only cop register is used to prevent a cop timer reset. this location contains user-de?ned rom data. figure 4-1 shows the cop register. use the following formula to calculate the cop timeout period: where cop timeout period 131 072 , f bus --------------------- - = f bus crystal frequency 2 -------------------------------------- =
motorola MC68HC05P9AD/d 7. page 5-2, figure 5-1. memory map change the user vectors portion at the bottom of the map as follows: from: figure 5-1. memory map to : figure 5-1. memory map 8. page 5-4, section 5.1.3 rom change the ?rst paragraph as follows: from: on-chip user rom includes 48 bytes at addresses $0020C$004f, 2048 bytes at $0100C$08ff, and 16 bytes at $1ff0C$1fff that contain user-de?ned vectors for servicing interrupts and resets. user vectors (rom) 16 bytes cop register? timer interrupt vector (high byte) timer interrupt vector (low byte) external interrupt vector (high byte) external interrupt vector (low byte) software interrupt vector (high byte) software interrupt vector (low byte) reset vector (high byte) reset vector (low byte) $1ff0 $1ffd $1ffc $1ffb $1ffa $1ff9 $1ff8 $1fff $1ffe $1fff $1ff0 ?writing 0 to bit 0 of $1ff0 clears cop timer. reading $1ff0 returns user rom data. user rom 8 bytes user vectors (rom) 8 bytes timer interrupt vector (high byte) timer interrupt vector (low byte) external interrupt vector (high byte) external interrupt vector (low byte) software interrupt vector (high byte) software interrupt vector (low byte) reset vector (high byte) reset vector (low byte) reserved $1ffd $1ffc $1ffb $1ffa $1ff9 $1ff8 $1fff $1ffe $1fff $1ff8 $1ff7 cop register* $1ff1 $1ff0 *writing zero to bit 0 of $1ff0 clears the cop timer.
MC68HC05P9AD/d motorola to : on-chip user rom includes 48 bytes at addresses $0020C$004f, 2048 bytes at $0100C$08ff, and 8 bytes at $1ff8C$1fff that contain user-de?ned vectors for servicing interrupts and resets. 9. page 7-3, section 7.2 siop pin descriptions add the following note after the last paragraph: n o te enabling and then disabling the siop configures data direction register b for siop operation and can also change the port b data register. after disabling the siop, initialize data direction register b and the port b data register as your application requires. 10. page 7-4, section 7.2.3 siop data output change the paragraph as follows: from: the sdo pin becomes a serial output and goes to a logical one as soon as the siop is enabled. between transfers, the state of the sdo pin re?ects the value of the last bit received on the previous transmission. sdo cannot be used as a standard output while the siop is enabled, because it is coupled to the last stage of the serial shift register. on the ?rst falling edge of sck, the ?rst data bit to be shifted out is presented to the sdo pin. to : enabling the siop con?gures the sdo pin as an output. the state of the sdo pin: ? is logic one if the siop has not been used since the last reset ? reflects the last bit received if the siop has been used since the last reset ? is unpredictable if sck was low during reset or if sck went low after reset between transfers, the state of the sdo pin re?ects the value of the last bit received on the previous transmission. sdo cannot be used as a standard output while the siop is enabled, because it is coupled to the last stage of the serial shift register. on the ?rst falling edge of sck, the ?rst data bit to be shifted out is presented to the sdo pin.
motorola MC68HC05P9AD/d 11. page 8-1, section 8.1 adc operation change the second paragraph as follows: from: a multiplexer selects one of four analog input channels (an3, an2, an1, or an0) for sampling. a comparator successively compares the output of an internal d/a converter to the sampled analog input. control logic changes the d/a conver ter input one bit at a time, starting with the msb, until the d/a converter output matches the sampled analog input. the conversion is monotonic and has no missing codes. to : a multiplexer selects one of four analog input channels (an0, an1, an2, or an3) for sampling. the conversion takes 32 cycles. the ?rst 12 cycles sample the voltage on the selected input pin by charging an internal capacitor. in the last 20 cycles, a comparator successively compares the output of an internal d/a converter to the sampled analog input. control logic changes the d/a converter input one bit at a time, starting with the msb, until the d/a converter output matches the sampled analog input. the conversion is monotonic and has no missing codes. at the end of the conversion, the conversion complete ?ag (cc) becomes set, and the cpu takes 2 cycles to move the result to the adc data register (addr). 12. page 8-2, section 8.2 a/d status and control register (adscr) change the ccf bit description as follows: from: ccf conversion complete flag this read-only bit is automatically set when an analog-to-digital conversion is complete, and a new result can be read from the a/d data register. ccf is automatically cleared when a new conversion begins or when either the a/d status and control register or the a/d data register is accessed. writing to or reading the a/d status and control register or the a/d data register starts a new conversion sequence. data from the previous conversion is overwritten regardless of the state of the ccf bit. while ccf is a logical zero, the requested a/d result is not yet available in the a/d data register. to : ccf conversion complete flag this read-only bit is automatically set when an analog-to-digital conversion is complete, and a new result can be read from the a/d data register. clear the ccf bit by writing to the a/d data register or by reading the a/d data register. reset clears the ccf bit.
MC68HC05P9AD/d motorola 13. page 10-7, table 10-5. a/d converter characteristics change the max column in the second row of table 10-5 as follows: from: to : 14. page 10-8, figure 10-6. tcap timing change the t tltl parameter to t ilil as follows: from: figure 10-6. tcap timing to : figure 10-6. tcap timing table 10-5. a/d converter characteristics characteristic min max unit absolute accuracy (4.0 > v rh > v dd ) (refer to note 1) 1-1/2 lsb table 10-5. a/d converter characteristics characteristic min max unit absolute accuracy (4.0 > v rh > v dd ) (refer to note 1) 1.5 lsb t tltl t th t tl t ilil t th t tl
motorola MC68HC05P9AD/d 15. page 10-12, table 10-8. siop timing (v dd = 5.0 vdc) change the ?rst row as follows: from: to : change note 1 at the bottom of the table as follows: from: 1. f op = f osc ? 2 = 2.1 mhz maximum; t cyc = 1 ? f op to : 1. f osc = crystal frequency; f op = f osc ? 2; t cyc = 1 ? f op (see table 10-6. control timing (v dd = 5.0 vdc).) delete note 2 at the bottom of the table. table 10-8. siop timing (v dd = 5.0 vdc) characteristic symbol min max unit frequency of operation master slave f siop ( m ) f siop ( s ) 0.25 dc 0.25 525 f op khz table 10-8. siop timing (v dd = 5.0 vdc) characteristic symbol min max unit frequency of operation master slave f siop ( m ) f siop ( s ) f osc /64 dc f osc /8 525 mhz khz
MC68HC05P9AD/d motorola 16. page 10-13, table 10-9. siop timing (v dd = 3.3 vdc) change the ?rst row as follows: from: to : change the note at the bottom of the table as follows: from: note: f op = 1.0 mhz maximum to : note: f osc = crystal frequency; f op = f osc ? 2; t cyc = 1 ? f op (see table 10-7. control timing (v dd = 3.3 vdc).) table 10-9. siop timing (v dd = 3.3 vdc) characteristic symbol min max unit frequency of operation master slave f siop ( m ) f siop ( s ) 0.25 dc 0.25 250 f op khz table 10-9. siop timing (v dd = 3.3 vdc) characteristic symbol min max unit frequency of operation master slave f siop ( m ) f siop ( s ) f osc /64 dc f osc /8 250 mhz khz
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